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well, no
i do RF then signal, and then wish i had done power

Posted by renesis at 19:44 | permalink | 0 comments


like he even knows
timecop: looks much better
timecop: signal and RF looks pretty predictable, id do power

Posted by renesis at 19:39 | permalink | 0 comments


ha
i tried to paste from .brd to .lib
and it said SKIPPING UNSUITABLE OBJECTS!
and only pasted the copper layers

Posted by renesis at 13:15 | permalink | 0 comments


info tool

Posted by renesis at 13:03 | permalink | 0 comments


this iswhy it shouldnt bea problem
because theres enough space
you might haveto split the chips more
i would actually pull them apart or off board and then bring them together after routing stuff close to them
wha happen
heh

Posted by renesis at 12:56 | permalink | 0 comments


do it better it just looks like you started
subgroup the groups
space doesnt look like itll be a problem, you just have to string a ton of passives together

Posted by renesis at 12:45 | permalink | 0 comments


hey where is dx
P3280 MATH 240 3 A
\o/
yeh =\
i havent gotten my psych grade yet
i dont really dont have 3 degrees unless he passes me =\
hahaha
tc it doesnt look so hard
fool
group all subcircuits

Posted by renesis at 12:40 | permalink | 0 comments


bukkake is a noodle dish
figure it out

Posted by renesis at 12:34 | permalink | 0 comments


oh hi
i gotta go =\

Posted by renesis at 02:33 | permalink | 0 comments


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